It is known that high performance field effect transistors (FETs) can be formed in fin-like semiconductor structures, commonly referred to as “FIN-FETs”. Integrated circuits (ICs) are fabricated using such FIN-FETS. Unlike conventional planar FETs, with FIN-FETs the semiconductor region containing the source-drain channel has a fin-like shape standing approximately perpendicular to the surface of the substrate die or wafer on which the device is formed. Gate electrodes can be provided on both exposed sides of the fin-like channel region and sometimes along the narrow top edge and even along the narrow bottom edge, although such edge gates are not required. The term “tri-gate” is used to refer to fin-type FETs that have the gate along the narrow top edge as well as along the sides. As used herein, the term “FIN-FET”, singular or plural, is intended to include all such variations.
The channel width W of a FIN-FET is primarily determined by the height H of the fin above the supporting substrate multiplied by the number of fins electrically connected in parallel in the FIN-FET. For a single fin FIN-FET, W≈H and for a FIN-FET having j parallel connected fins, W≈j*H, j=1, 2, 3, . . . N. The channel length L is substantially determined by the distance along the length of the fin(s), usually substantially parallel to the supporting substrate, between the source and drain where the opposing sides of the fin are covered by the gate electrode. Because of the distinctly different geometry of a FIN-FET compared to a planar FET, designing and constructing FIN-FETS and ICs embodying FIN-FETs to meet specific performance criteria present special challenges. These challenges are especially difficult when it is desired to form both multiple fin height FIN-FETs and planar FETs on the same substrate.